High-speed VLSI arithmetic processor architectures using hybrid number representation
Author:
Publisher
Springer Science and Business Media LLC
Subject
Electrical and Electronic Engineering,Information Systems,Signal Processing
Link
http://link.springer.com/content/pdf/10.1007/BF00925121.pdf
Reference25 articles.
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5. A. Vandemeulebroecke, E. Vanzieleghme, T. Denayer, P.G.A. Jespers, “A new carry-free division algorithm and its application to a single-chip 1024-b RSA Processor,”IEEE Journal of Solid-State Circuits, vol. 25, 1990, pp. 748–756.
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