VLSI generalised digit serial architecture for multiplication, division and square root-Reference-Cited by-同舟云学术

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VLSI generalised digit serial architecture for multiplication, division and square root

Published:1999-12 Issue:3 Volume:79 Page:261-272
ISSN:0165-1684
Container-title:Signal Processing
language:en
Short-container-title:Signal Processing

Author:

Bashagha A.E

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Computer Vision and Pattern Recognition,Signal Processing,Software,Control and Systems Engineering

Reference25 articles.

1. Bit Level pipelined digit serial array processors;Aggoun;IEEE Trans. Circuits Systems,1998

2. Design methodology for subdigit pipelined digit-serial IIR filters;Aggoun;Signal Processing,1998

3. High speed arithmetic arrays;Agrawal;IEEE Trans. Comput.,1979

4. Introduction to the role of redundancy in computer arithmetic;Atkins;IEEE Comput. J.,1975

5. Signed digit number representations for fast parallel arithmetic;Avizienis;IRE Trans. Comput.,1961

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Pipelined area-efficient digit serial divider;Signal Processing;2003-09

2. Novel radix-2k square root module;IEE Proceedings - Circuits, Devices and Systems;2001

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