The multi-dataflow composer tool: generation of on-the-fly reconfigurable platforms-Reference-Cited by-同舟云学术

The multi-dataflow composer tool: generation of on-the-fly reconfigurable platforms

Published:2012-11-10 Issue:1 Volume:9 Page:233-249
ISSN:1861-8200
Container-title:Journal of Real-Time Image Processing
language:en
Short-container-title:J Real-Time Image Proc

Author:

Palumbo Francesca,Carta Nicola,Pani Danilo,Meloni Paolo,Raffo Luigi

Publisher

Springer Science and Business Media LLC

Subject

Information Systems

Link

http://link.springer.com/content/pdf/10.1007/s11554-012-0284-3.pdf

Reference23 articles.

1. Altera Corp: FPGA run-time reconfiguration: two approaches—white paper (2008)

2. Angermeier J., Wildermann S., Sibirko E., Teich J.: Placing streaming applications with similarities on dynamically partially reconfigurable architectures. In: International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2010. pp. 91–96 (2010)

3. Carta, S.M., Pani, D., Raffo, L.: Reconfigurable coprocessor for multimedia application domain. J. VLSI Signal Process. Syst. 44, 135–152 (2006)

4. Compton, K., Hauck, S.: Reconfigurable computing: a survey of systems and software. ACM Comput. Surv. 34, 171–210 (2002)

5. Graphiti Editor. http://sourceforge.net/apps/trac/graphiti-editor/

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