Related Work
Author:
Publisher
Springer International Publishing
Link
http://link.springer.com/content/pdf/10.1007/978-3-319-32094-6_8
Reference48 articles.
1. Rixner S, Dally WJ, Kapasi UJ, Mattson P, Owens JD (2000) Memory access scheduling. In: International symposium on computer architecture (ISCA), pp 128–138
2. Dodd J (2006) Adaptive page management. US Patent 7,076,617
3. Mutlu O, Moscibroda T (2008) Parallelism-aware batch scheduling: enhancing both performance and fairness of shared DRAM systems. SIGARCH Comput Architect News 36(3)
4. Stuecheli J, Kaseridis D, Daly D, Hunter HC, John LK (2010) The virtual write queue: coordinating DRAM and last-level cache policies. SIGARCH Comput Architect News 38(3):72–82
5. Ipek E, Mutlu O, Martinez J, Caruana R (2008) Self-optimizing memory controllers: a reinforcement learning approach. In: International symposium on computer architecture (ISCA), pp 39–50
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