Post-Silicon SoC Validation Challenges
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Publisher
Springer International Publishing
Link
http://link.springer.com/content/pdf/10.1007/978-3-319-98116-1_1
Reference37 articles.
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3. P. Behnam, B. Alizadeh, S. Taheri, M. Fujita., Formally analyzing fault tolerance in datapath designs using equivalence checking. In 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC). (IEEE, 2016), pp. 133–138
4. S. Chandran, P.R. Panda, S.R. Sarangi, A. Bhattacharyya, D. Chauhan, S. Kumar, Managing trace summaries to minimize stalls during postsilicon validation. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 25(6), 1881–1894 (2017)
5. D. Chatterjee, C. McCarter, V. Bertacco, Simulation-based signal selection for state restoration in silicon debug, in Proceedings of the International Conference on Computer-Aided Design. (IEEE Press, 2011), pp. 595–601
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