1. Czajkowski, T.S., Neto, D., Kinsner, M., Aydonat, U., Wong, J., Denisenko, D., Yiannacouras, P., Freeman, J., Singh, D.P., Brown, S.D.: OpenCL for FPGAs: Prototyping a Compiler, International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), pp. 3–12 (2012)
2. Dohi, K., Okina, K., Soejima, R., Shibata, Y., Oguri, K.: Performance modeling of stencil computing on a stream-based FPGA accelerator for efficient design space exploration. IEICE Trans. Inf. Syst. E98-D(2), 298–308 (2015)
3. Khronos Group: The open standard for parallel programming of heterogeneous systems. https://www.khronos.org/opencl/
4. Intel: SDK for OpenCL. https://www.altera.com/products/design-software/embedded-software-developers/opencl/overview.html
5. Jia, Q., Zhou, H.: Tuning stencil codes in OpenCL for FPGAs. In: IEEE 34th International Conference on Computer Design (ICCD), pp. 249–256 (2016)