Quantitative Optimization and Early Cost Estimation of Low-Power Hierarchical-Architecture SRAMs Based on Accurate Cost Models
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Publisher
Springer International Publishing
Link
http://link.springer.com/content/pdf/10.1007/978-3-319-23799-2_4
Reference10 articles.
1. Sharma, V., et al.: A 4.4 pJ/access 80 MHz, 128 kbit variability resilient SRAM with Multi-Sized sense amplifier redundancy. IEEE J. Solid-State Circuits 46(10), 2416–2430 (2011)
2. Clerc, S., et al.: A 65 nm SRAM achieving 250 mV retention and 350 mV, 1 MHz, 55fJ/bit access energy, with bit-interleaved radiation soft error tolerance. In: 2012 Proceedings of the ESSCIRC (ESSCIRC), pp. 313–316. IEEE (2012)
3. Rooseleer, B., Dehaene, W.: A 40 nm, 454 MHz 114 fJ/bit area-efficient SRAM memory with integrated charge pump. In: 2013 Proceedings of the ESSCIRC (ESSCIRC), pp. 201–204. IEEE (2013)
4. Ren, Y., Noll, T.G.: An accurate power estimation model for low-power hierarchical-architecture SRAMs. In: 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC), pp. 144–149.IEEE (2013)
5. Ren, Y., et al.: Low power 6T-SRAM with tree address decoder using a new equalizer precharge scheme. In: 2012 IEEE International SOC Conference (SOCC), pp. 224–229. IEEE (2012)
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