A 65nm SRAM achieving 250mV retention and 350mV, 1MHz, 55fJ/bit access energy, with bit-interleaved radiation Soft Error tolerance
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Publisher
IEEE
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http://xplorestaging.ieee.org/ielx5/6331297/6341242/06341317.pdf?arnumber=6341317
Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Area-efficient fully digital memory using minimum height standard cells for near-threshold voltage computing;Integration;2019-03
2. A 32 kb 0.35–1.2 V, 50 MHz–2.5 GHz Bit-Interleaved SRAM With 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS;IEEE Transactions on Circuits and Systems I: Regular Papers;2017-09
3. Ultra Low Voltage Synthesizable Memories: A Trade-Off Discussion in 65 nm CMOS;IEEE Transactions on Circuits and Systems I: Regular Papers;2016-06
4. Memories for NTC;Near Threshold Computing;2016
5. Quantitative Optimization and Early Cost Estimation of Low-Power Hierarchical-Architecture SRAMs Based on Accurate Cost Models;IFIP Advances in Information and Communication Technology;2015
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