Author:
Rooseleer Bram,Dehaene Wim
Cited by
12 articles.
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1. Buried Interconnects for Sub-5 nm SRAM Design;IEEE Transactions on Electron Devices;2022-03
2. SiO2-Based Conductive-Bridging Random Access Memory;Resistive Switching: Oxide Materials, Mechanisms, Devices and Operations;2021-10-16
3. Bottom-Up Approach for High Speed SRAM Word-line Buffer Insertion Optimization;2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC);2019-10
4. Optical memory architectures for fast routing address look-up (AL) table operation;Journal of Physics: Photonics;2019-10-01
5. Synthesizable Memory Arrays Based on Logic Gates for Subthreshold Operation in IoT;IEEE Transactions on Circuits and Systems I: Regular Papers;2019-03