Robust Application Scheduling with Adaptive Parallelism in Dark-Silicon Constrained Multicore Systems-Reference-Cited by-同舟云学术

Robust Application Scheduling with Adaptive Parallelism in Dark-Silicon Constrained Multicore Systems

Published:2017 Issue: Volume: Page:217-236
ISSN:
Container-title:The Dark Side of Silicon
language:
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Author:

Kapadia Nishit,Pasricha Sudeep

Publisher

Springer International Publishing

Link

http://link.springer.com/content/pdf/10.1007/978-3-319-31596-6_8

Reference40 articles.

1. A. Kaouache, F. Wrobel, F. Saigne, A.D. Touboul, R.D. Schrimpf, Analytical method to evaluate soft error rate due to alpha contamination. IEEE Trans. Nucl. Sci. 60(6), 4059–4066 (2013)

2. N. Gaspard, S. Jagannathan, Z. Diggins, A.V. Kauppila, T.D. Loveless, J.S. Kauppila, B.L. Bhuva, L.W. Massengill, W.T. Holman, Effect of threshold voltage implants on single-event error rates of D flip-flops in 28-nm bulk CMOS. IEEE International Reliability Physics Symposium, Apr 2013, pp. SE.7.1–SE.7.3

3. S. Abe, Y. Watanabe, N. Shibano, N. Sano, H. Furuta, M. Tsutsui, T. Uemura, T. Arakawa, Neutron-induced soft error analysis in MOSFETs from a 65 to a 25 nm design rule using multi-scale Monte-Carlo simulation method. IEEE International Reliability Physics Symposium, Apr 2012, pp. SE.3.1–SE.3.6

4. D. Zhu, R. Melhem, D. Mosse, The effects of energy management on reliability in real-time embedded systems. IEEE/ACM International Conference on Computer Aided Design (ICCAD), San Jose, California, Nov 2004, pp. 35–40

5. T.D. Loveless, S. Jagannathan, T. Reece, J. Chetia, B.L. Bhuva, M.W. McCurdy, L.W. Massengill, S.J. Wen, R. Wong, D. Rennie, Neutron- and proton-induced single event upsets for D- and DICE-flip/flop designs at a 40 nm technology node. IEEE Trans. Nucl. Sci. 58(3), 1008–1014 (2011)