Effect of threshold voltage implants on single-event error rates of D flip-flops in 28-nm bulk CMOS-Reference-Cited by-同舟云学术

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Effect of threshold voltage implants on single-event error rates of D flip-flops in 28-nm bulk CMOS

Published:2013-04 Issue: Volume: Page:
ISSN:
Container-title:2013 IEEE International Reliability Physics Symposium (IRPS)
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Author:

Gaspard N.,Jagannathan S.,Diggins Z.,Kauppila A. V.,Loveless T. D.,Kauppila J. S.,Bhuva B. L.,Massengill L. W.,Holman W. T.,Oates A. S.,Fang Y.,Wen S.,Wong R.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/6523362/6531927/06532114.pdf?arnumber=6532114

Cited by 4 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Single-Event Performance of Flip Flop Designs at the 5-nm Bulk FinFET Node at Near-Threshold Supply Voltages;2024 IEEE International Reliability Physics Symposium (IRPS);2024-04-14

2. Analysis of Single-Event Upsets and Transients in 22 nm Fully Depleted Silicon-On-Insulator Logic;IEEE Transactions on Nuclear Science;2023-04

3. SE Performance of D-FF Designs With Different V _T Options at Near-Threshold Supply Voltages in 7-nm Bulk FinFET Technology;IEEE Transactions on Nuclear Science;2022-07

4. Robust Application Scheduling with Adaptive Parallelism in Dark-Silicon Constrained Multicore Systems;The Dark Side of Silicon;2017

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