Design Case
Author:
Publisher
Springer International Publishing
Link
http://link.springer.com/content/pdf/10.1007/978-3-319-62012-1_7
Reference8 articles.
1. B.G. Lee, B.M. Min, G. Manganaro, J.W. Valvano, A 14-b 100-ms/s pipelined adc with a merged sha and first mdac. IEEE J. Solid-State Circuits 43, 2613–2619 (2008). Dec
2. H.V. de Vel, B. Buter, H. van der Ploeg, M. Vertregt, G. Geelen, E. Paulus, A 1.2v 250 mw 14b 100ms/s digitally calibrated pipeline adc in 90nm cmos, in 2008 IEEE Symposium on VLSI Circuits (June 2008), pp. 74–75
3. A.M.A. Ali, H. Dinc, P. Bhoraskar, C. Dillon, S. Puckett, B. Gray, C. Speir, J. Lanford, D. Jarman, J. Brunsilius, P. Derounian, B. Jeffries, U. Mehta, M. McShea, H.Y. Lee, 29.3 a 14b 1gs/s rf sampling pipelined adc with background calibration, in 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) (Feb 2014), pp. 482–483
4. A. Panigada, I. Galton, A 130mw 100ms/s pipelined adc with 69db sndr enabled by digital harmonic distortion correction, in 2009 IEEE International Solid-State Circuits Conference—Digest of Technical Papers (Feb 2009), pp. 162–163, 163a
5. B. Peng, G. Huang, H. Li, P. Wan, P. Lin, A 48-mw, 12-bit, 150-ms/s pipelined adc with digital calibration in 65 nm cmos, in 2011 IEEE Custom Integrated Circuits Conference (CICC) (Sept 2011), pp. 1–4
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