A 1.2V 250mW 14b 100MS/s digitally calibrated pipeline ADC in 90nm CMOS

Author:

Van de Vel Hans,Berry Buter ,van der Ploeg Hendrik,Vertregt Maarten,Geelen Govert,Paulus Edward

Publisher

IEEE

Cited by 10 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Design Case;Analog Circuits and Signal Processing;2017-08-03

2. Amplification;Analog Circuits and Signal Processing;2017-08-03

3. A 12 bit 200 MS/s Zero-Crossing-Based Pipelined ADC With Early Sub-ADC Decision and Output Residue Background Calibration;IEEE Journal of Solid-State Circuits;2014-06

4. A Power-Optimized High-Speed and High-Resolution Pipeline ADC with a Parallel Sampling First Stage for Broadband Multi-Carrier Systems;Design, Modeling and Testing of Data Converters;2013-10-06

5. A Range-Scaled 13b 100 MS/s 0.13 um CMOS SHA-Free ADC Based on a Single Reference;JSTS:Journal of Semiconductor Technology and Science;2013-04-30

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