Reduced latency DRAM for multi-core safety-critical real-time systems-Reference-Cited by-同舟云学术

Reduced latency DRAM for multi-core safety-critical real-time systems

Published:2019-09-10 Issue:2 Volume:56 Page:171-206
ISSN:0922-6443
Container-title:Real-Time Systems
language:en
Short-container-title:Real-Time Syst

Author:

Hassan Mohamed^ORCID

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering,Control and Optimization,Computer Networks and Communications,Computer Science Applications,Modeling and Simulation,Control and Systems Engineering

Link

http://link.springer.com/content/pdf/10.1007/s11241-019-09338-8.pdf

Reference44 articles.

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3. Ecco L, Ernst R (2015) Improved DRAM timing bounds for real-time DRAM controllers with read/write bundling. In: Real-time systems symposium, pp 53–64

4. Ecco L, Ernst R (2017) Tackling the bus turnaround overhead in real-time SDRAM controllers. IEEE Trans Comput 66(11):1961–1974

5. Ecco L, Tobuschat S, Saidi S, Ernst R (2014) A mixed critical memory controller using bank privatization and fixed priority scheduling. In: IEEE international conference on embedded and real-time computing systems and applications (RTCSA)

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