Challenges in Design, Data Placement, Migration and Power-Performance Trade-offs in DRAM-NVM-based Hybrid Memory Systems
Author:
Affiliation:
1. Department of Computer Science & Engineering, National Institute of Technology Karnataka, 575025 Surathkal, India
Publisher
Informa UK Limited
Subject
Electrical and Electronic Engineering
Link
https://www.tandfonline.com/doi/pdf/10.1080/02564602.2022.2127945
Reference92 articles.
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2. B. Pourshirazi and Z. Zhu, “Refree: a refresh-free hybrid DRAM/PCM main memory system,” in 2016 IEEE International Parallel and Distributed Processing Symposium (IPDPS), 2016. pp. 566–75.
3. R. Salkhordeh and H. Asadi, “An operating system level data migration scheme in hybrid DRAM-NVM memory architecture,” in 2016 Design, Automation Test in Europe Conference Exhibition (DATE), 2016. pp. 936–41.
4. D. Ustiugov, A. Daglis, J. Picorel, M. Sutherland, E. Bugnion, B. Falsafi, and D. Pnevmatikatos, “Design guidelines for high-performance SCM hierarchies,” in Proceedings of the International Symposium on Memory Systems. MEMSYS ‘18, New York, NY: Association for Computing Machinery, 2018, pp. 3–16.
5. Energy-aware page replacement and consistency guarantee for hybrid NVM–DRAM memory systems
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