Memristor-Based Multiplier and Squarer of Some Numbers of the form 10 l ± m
Author:
Publisher
Springer Science and Business Media LLC
Subject
Electrical and Electronic Engineering,General Computer Science
Link
https://link.springer.com/content/pdf/10.1007/s40031-022-00717-7.pdf
Reference18 articles.
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3. J. A. Pineiro, M. D. Ercegovac, and J. D. Bruguera, Algorithm and architecture for logarithm, exponential and powering computation. IEEE Trans. on Computers, pp. 1085–1096, (2004)
4. S. Gao, D. Al-Khalili, J. M. Pierre Langlois and N. Chabini, Efficient realization of BCD multipliers using FPGAs. Hindawai Int. Journal of Reconfigurable Computing, vol. 20, pp. 1–12 (2017)
5. G. Jaberipur, A. Kaivani, Binary-coded decimal digit multipliers. IET Comput. Digital Tech. 1(4), 377–381 (2007)
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