A New Squarer design with reduced area and delay-Reference-Cited by-同舟云学术

A New Squarer design with reduced area and delay

Published:2016-09 Issue:5 Volume:10 Page:205-214
ISSN:1751-8601
Container-title:IET Computers & Digital Techniques
language:en
Short-container-title:IET Computers & Digital Techniques

Author:

Banerjee Arindam¹,Das Debesh Kumar²

Affiliation:

1. Department of ECEJIS College of EngineeringKalyaniNadiaWest BengalIndia

2. Department of CSEJadavpur UniversityJadavpurKolkataWest BengalIndia

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1049/iet-cdt.2015.0170

Reference15 articles.

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5. Kwon T.J. Sondeen J. Draper J.: ‘Floating‐point division and square root using a Taylor‐series expansion algorithm’.Proc. IEEE Int. Midwest Symp. Circuits and Systems 2007 pp.305–308

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