Additional optimizations for parallel squarer units
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/6852006/6865048/06865140.pdf?arnumber=6865140
Cited by 12 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. AxRSU-$$2^{m}$$: Higher-Order m-Bit Approximate Encoders for Radix-$$2^{m}$$ Squarer Units;Circuits, Systems, and Signal Processing;2024-02-26
2. Design of Radix-8 Based Approximate Booth Squarer for Error Tolerant Computing;2023 International Conference on Next Generation Electronics (NEleX);2023-12-14
3. Approximate squaring circuits exploiting recursive architectures;Integration;2023-07
4. VLSI Architectures of Approximate Arithmetic Units Applied to Parallel Sensors Calibration;IEEE Transactions on Circuits and Systems I: Regular Papers;2023
5. Energy-Efficient VLSI Squarer Unit with Optimized Radix-2m Multiplication Logic;Circuits, Systems, and Signal Processing;2022-11-22
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