Exploring Area/Delay Tradeoffs in an AES FPGA Implementation-Reference-Cited by-同舟云学术

Exploring Area/Delay Tradeoffs in an AES FPGA Implementation

Published:2004 Issue: Volume: Page:575-585
ISSN:0302-9743
Container-title:Field Programmable Logic and Application
language:
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Author:

Zambreno Joseph,Nguyen David,Choudhary Alok

Publisher

Springer Berlin Heidelberg

Link

http://link.springer.com/content/pdf/10.1007/978-3-540-30117-2_59.pdf

Reference15 articles.

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3. Lecture Notes in Computer Science;G.P. Saggese,2003

4. Kaps, J.-P., Paar, C.: Fast DES implementation for FPGAs and its application to a universal key-search machine. In: Proc. of the 5th Annual Workshop on Selected Areas in Cryptography (SAC), pp. 234–247 (1998)

5. Lecture Notes in Computer Science;I. Gonzalez,2003

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