An FPGA-Based Performance Analysis of the Unrolling, Tiling, and Pipelining of the AES Algorithm-Reference-Cited by-同舟云学术

An FPGA-Based Performance Analysis of the Unrolling, Tiling, and Pipelining of the AES Algorithm

Published:2003 Issue: Volume: Page:292-302
ISSN:0302-9743
Container-title:Field Programmable Logic and Application
language:
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Author:

Saggese G. P.,Mazzeo A.,Mazzocca N.,Strollo A. G. M.

Publisher

Springer Berlin Heidelberg

Link

http://link.springer.com/content/pdf/10.1007/978-3-540-45234-8_29

Reference10 articles.

1. Daemen, J., Rijmen, V.: AES Proposal: Rijndael, AES Algorithm Submission (September 1999), available at http://www.nist.gov/CryptoToolkit

2. National Institute of Standards and Technology (NIST), FIPS Publication 197. Advanced Encryption Standard (AES) (November 2001)

3. Menezes, A., van Oorschot, P., Vanstone, S.: Handbook of Applied Cryptography. CRC Press, Boca Raton (1996)

4. National Institute of Standards and Technology (NIST), Special Publication 800-38A. Recommendation for Block Cipher Modes of Operation (December 2001)

5. Weaver, N., Wawrzynek, J.: Very High Performance, Compact AES Implementation in Xilinx FPGAs (September 2002), available at http://www.cs.berkeley.edu/~nweaver/sfra/rijndael.pdf

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