Multi-gigabit GCM-AES Architecture Optimized for FPGAs-Reference-Cited by-同舟云学术

Multi-gigabit GCM-AES Architecture Optimized for FPGAs

Published: Issue: Volume: Page:227-238
ISSN:0302-9743
Container-title:Cryptographic Hardware and Embedded Systems - CHES 2007
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Author:

Lemsitzer Stefan,Wolkerstorfer Johannes,Felber Norbert,Braendli Matthias

Publisher

Springer Berlin Heidelberg

Link

http://link.springer.com/content/pdf/10.1007/978-3-540-74735-2_16.pdf

Reference20 articles.

1. NIST: Advanced Encryption Standard (AES). Federal Information Processing Standards Publication 197 (2001), http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf

2. Dworkin, M.: Recommendation for Block Cipher Modes of Operation. NIST Special Publication 800-38A (2001)

3. NIST: CSRC Proposed Modes of Operation (March 2007), http://csrc.nist.gov/CryptoToolkit/modes/proposedmodes/index.html

4. Hodjat, A., Verbauwhede, I.: A 21.54 Gbits/s Fully Pipelined AES Processor on FPGA. In: Field-Programmable Custom Computing Machines, 2004. FCCM 2004. 12th Annual IEEE Symposium on (2004)

5. Moroioka, S., Satoh, A.: A 10 Gbps Full-AES Crypto Design with a Twisted-BDD S-Box architecture. In: ICCD 2002. Proceedings of the 2002 IEEE International Conference on Computer Design, IEEE Computer Society Press, Los Alamitos (2002)

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