Pushing AES-256-GCM to Limits: Design, Implementation and Real FPGA Tests
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Publisher
Springer Nature Switzerland
Link
https://link.springer.com/content/pdf/10.1007/978-3-031-61486-6_18
Reference12 articles.
1. Buhrow, B., Fritz, K., Gilbert, B., Daniel, E.: A highly parallel AES-GCM core for authenticated encryption of 400 GB/s network protocols. In: 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig), pp. 1–7 (2015). https://doi.org/10.1109/ReConFig.2015.7393321
2. Henzen, L., Fichtner, W.: FPGA parallel-pipelined AES-GCM core for 100g ethernet applications. In: 2010 Proceedings of ESSCIRC, pp. 202–205 (2010). https://doi.org/10.1109/ESSCIRC.2010.5619894
3. Hodjat, A., Verbauwhede, I.: Area-throughput trade-offs for fully pipelined 30 to 70 Gbits/s AES processors. IEEE Trans. Comput. 55(4), 366–372 (2006). https://doi.org/10.1109/TC.2006.49
4. Lecture Notes in Computer Science;S Lemsitzer,2007
5. Malina, L., Cibik, P., Jedlicka, P., Smekal, D., Ricci, S., Hrabovsky, J.: Hardware-based cryptographic accelerator for post quantum era. In: 2021 13th International Congress on Ultra Modern Telecommunications and Control Systems and Workshops (ICUMT), pp. 149–155 (2021). https://doi.org/10.1109/ICUMT54235.2021.9631686
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