200 Gbps Hardware Accelerated Encryption System for FPGA Network Cards
Author:
Affiliation:
1. Brno University of Technology, Brno, Czech Rep
2. Netcope Technologies, Brno, Czech Rep
3. KU Leuven, Leuven, Belgium
Funder
National Sustainability Program
Ministry of Interior of the Czech Republic
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/3266444.3266446
Reference24 articles.
1. Morris J Dworkin. 2007. Recommendation for block cipher modes of operation: Galois/Counter Mode (GCM) and GMAC. Special Publication (NIST SP)-800--38D (2007). Morris J Dworkin. 2007. Recommendation for block cipher modes of operation: Galois/Counter Mode (GCM) and GMAC. Special Publication (NIST SP)-800--38D (2007).
2. FPGA based fast and high-throughput 2-slow retiming 128-bit AES encryption algorithm
3. Comparative analysis of different AES implementation techniques for efficient resource usage and better performance of an FPGA
4. PUB FIPS. {n. d.}. 197 Advanced Encryption Standard (AES) National Institute of Standards and Technology US Department of Commerce November 2001. ({n. d.}). http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf PUB FIPS. {n. d.}. 197 Advanced Encryption Standard (AES) National Institute of Standards and Technology US Department of Commerce November 2001. ({n. d.}). http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf
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