Publisher
Springer Berlin Heidelberg
Reference13 articles.
1. Aagaard, M.D.: A Framework for the Specification, Design, and Verification of Pipelined Circuits. PhD thesis, School of Elect. Eng., Cornell Univ. (January 1995)
2. Aagaard, M.D.: A formal model and correctness statement for pipelined circuits. Technical report, E&CE, Univ. of Waterloo (April 2003)
3. Lecture Notes in Computer Science;M.D. Aagaard,2002
4. Lecture Notes in Computer Science;T. Arons,2000
5. Lecture Notes in Computer Science;J.R. Burch,1994
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