Author:
Wang Wei,Hu Yu,Han Yin-He,Li Xiao-Wei,Zhang You-Sheng
Publisher
Springer Science and Business Media LLC
Subject
Computational Theory and Mathematics,Computer Science Applications,Hardware and Architecture,Theoretical Computer Science,Software
Reference31 articles.
1. Zorian Y. A distributed BIST control scheme for complex VLSI devices. In Proc. IEEE VLSI Test Symposium, Atlantic City, USA, IEEE Computer Society, 1993, pp.4–9.
2. Sinanoglu O, Orailoglu A. Scan power minimization through stimulus and response transformations. In Proc. IEEE/ACM Design, Automation and Test in Europe Conference, Paris, France, February 16–20, 2004, pp.404–409.
3. Zhang X D, Roy K. Peak power reduction in low power BIST. In Proc. IEEE International Symposium on Quality Electronic Design, San Jose, California, USA, March 20–22, 2000, pp.425–432.
4. Ghosh D, Bhunia S, Roy K. Multiple scan chain design technique for power reduction during test application in BIST. In Proc. IEEE Defect and Fault Tolerance in VLSI Systems, Boston, MA, USA, November 3–5, 2003, pp.191–198.
5. Chandra A, Chakrabarty K. Low-power scan testing and test data compression for system-on-a-chip. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, 2002, 21(5): 597–604.
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