Author:
Engelke Piet,Polian Ilia,Renovell Michel,Becker Bernd
Publisher
Springer Science and Business Media LLC
Subject
Electrical and Electronic Engineering
Reference24 articles.
1. J.P. Cusey and J.H. Patel, “BART: A Bridging Fault Test Generator for Sequential Circuits,” Int’l Test Conf., 1997, pp. 838–847.
2. P. Engelke, I. Polian, M. Renovell, and B. Becker, “Simulating Resistive Bridging and Stuck-At Faults,” Int’l Test Conf., 2003, pp. 1051–1059.
3. P. Engelke, I. Polian, M. Renovell, B. Seshadri, and B. Becker, “The Pros and Cons of Very-Low-Voltage Testing: An Analysis Based on Resistive Short Defects,” VLSI Test Symp., 2004, pp. 171–178.
4. F.J. Ferguson and J. Shen, “Extraction and Simulation of Realistic CMOS Faults using Inductive Fault Analysis,” Int’l Test Conf., 1988, pp. 475–484.
5. E. Gizdarski and H. Fujiwara, “SPIRIT: A Highly Robust Combinational test Generation Algorithm,” IEEE Trans. on CAD, vol. 21, no. 12, pp. 1446–1458, 2002.
Cited by
15 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献