A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and Systems

Author:

Tran D. A.,Virazel A.,Bosio A.,Dilillo L.,Girard P.,Pravossoudovich S.,Wunderlich H.–J.

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering

Reference26 articles.

1. Semiconductor Industry Association (SIA), “International Technology Roadmap for Semiconductors (ITRS)”, 2011

2. I. Koren, C. M. Krishna, “Fault-Tolerant Systems”, Ed. Organ Kaufmann, 2007

3. Nicolaidis M, Anghel L, Achouri N (2005) Memory defect tolerance architectures for nanotechnologies”. J of Electronic Testing 21(4):445–455

4. Chin-Lung Su, Yi-Ting Yeh, Cheng-Wen Wu, “An Integrated ECC and Redundancy Repair Scheme for Memory Reliability Enhancement”, Proc. of the 20th Int. Sym. on Defect and Fault-Tolerance in VLSI Systems (DFT’05), pg. 81–92, 2005

5. Lyons RE, Vanderkulk W (1962) The use of triple-Modular redundancy to improve computer reliability”. IBM J Res Dev 6(2):200–209

Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. SPLM: A Flexible and Accurate Reliability Assessment Model for Logic Circuits;Journal of Circuits, Systems and Computers;2018-11-12

2. Critical Gates Identification for Fault-Tolerant Design in Math Circuits;Journal of Electrical and Computer Engineering;2017

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