Low-Power Scan Testing: A Scan Chain Partitioning and Scan Hold Based Technique

Author:

Arvaniti Efi,Tsiatouhas Yiorgos

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering

Cited by 11 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A Modular Scan Design Verification approach for Multi-channel Mode;2022 IEEE 3rd International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI SATA);2022-12-15

2. Low-Power Scan Correlation-Aware Scan Cluster Reordering for Wireless Sensor Networks;Sensors;2021-09-12

3. A low-power True Single Phase Clock scan cell design for VLSI testing;Materials Today: Proceedings;2021

4. Reliable test architecture with test cost reduction for systolic based DNN accelerators;IEEE Transactions on Circuits and Systems II: Express Briefs;2021

5. Thermal-aware Test Data Compression for System-on-Chip Based on Modified Bitmask Based Methods;Journal of Electronic Testing;2020-10

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