Application of Machine Learning Techniques in Post-Silicon Debugging and Bug Localization
Author:
Publisher
Springer Science and Business Media LLC
Subject
Electrical and Electronic Engineering
Link
http://link.springer.com/article/10.1007/s10836-018-5716-y/fulltext.html
Reference32 articles.
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3. E. Singh, C. Barrett, S. Mitra, E-QED: electrical bug localization during post-silicon validation enabled by quick error detection and formal methods, In Computer aided verification, CAV 2017, pp. 104–125
4. S. Park, A. Bracy, H. Wang, S. Mitra, BLoG: post-silicon bug localization in processors using bug localization graphs, In Design Automation Conference, DAC 2010
5. A. DeOrio, D. S. Khudia, V. Bertacco, Post-silicon bug diagnosis with inconsistent executions, In the proceedings of IC Computer Aid Design ICCAD, 2011
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