Efficient Error-Tolerability Testing on Image Processing Circuits Based on Equivalent Error Rate Transformation-Reference-Cited by-同舟云学术

Efficient Error-Tolerability Testing on Image Processing Circuits Based on Equivalent Error Rate Transformation

Published:2014-11-05 Issue:6 Volume:30 Page:687-699
ISSN:0923-8174
Container-title:Journal of Electronic Testing
language:en
Short-container-title:J Electron Test

Author:

Hsieh Tong-Yu,Peng Yi-Han,Li Kuan-Hsien

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering

Link

http://link.springer.com/content/pdf/10.1007/s10836-014-5488-y.pdf

Reference20 articles.

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3. I. Chong and A. Ortega (2005) Hardware testing for error tolerant multimedia compression based on linear transforms. Proc. Int’l. Symp. on Defect and Fault Tolerance in VLSI Systems, pp. 523–531

4. C.-L. Hsu, Y.-S. Huang and T.-H. Liu (2008) SSD-based testing scheme for error tolerance analysis in H.264/AVC encoder. Proc. Int’l. Conf. on Communications, Circuits and Systems, pp. 684–688

5. H. Chung and A. Ortega (2005) Analysis and testing for error tolerant motion estimation. Proc. Int’l. Symp. on Defect and Fault Tolerance in VLSI Systems, pp. 514–522

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