A Tunable Concurrent BIST Design Based on Reconfigurable LFSR

Author:

Menbari Ahmad,Jahanirad HadiORCID

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering

Reference21 articles.

1. Abirami S, Paulin NS, S. Venkateshwaran SP (2015) A concurrent BIST architecture for online input vector monitoring. International Conference on Science, Technology and Management (ICSTM), New Delhi, India, pp 1411–1417

2. Abramovici M, Breuer M, Friedman A (1990) Digital Systems Testing and Testable Design. Computer Science Press

3. Askarzadeh M, Haghparast M, Jabbehdari S (2021) Power consumption reduction in built-in self-test circuits. J Ambient Intell Humaniz Comput 14:1109–1122

4. Biswas S, Das SR, Petriu EM (2006) Space compactor design in VLSI circuits based on graph theoretic concepts. IEEE Trans Instrum Meas 55(4):1106–1118

5. Divyapreethi B, Karthik T (2015) Input vector monitoring concurrent BIST architecture using modified SRAM cells. ARPN J Eng Appl Sci 10(9):4042–4046

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1. MBIST-HSIO Concurrent Testing Strategies and Test Challenges;2023 IEEE International Test Conference India (ITC India);2023-07-23

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