MBIST-HSIO Concurrent Testing Strategies and Test Challenges-Reference-Cited by-同舟云学术

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MBIST-HSIO Concurrent Testing Strategies and Test Challenges

Published:2023-07-23 Issue: Volume: Page:
ISSN:
Container-title:2023 IEEE International Test Conference India (ITC India)
language:
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Author:

Krishnan Boopala¹,Mishra Shalini¹,Emekar Sumit¹,M Subrahmanya¹,Ramanujam Prasanna¹,Cu Melvin²,Pu Linfeng³

Affiliation:

1. Qualcomm India Pvt Ltd,Bengaluru,India

2. Qualcomm Semiconductor Limited,Zhubei City,Taiwan

3. Qualcomm Global Trading Pte. Ltd,Singapore

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10235328/10235351/10235386.pdf?arnumber=10235386

Reference10 articles.

1. Dynamic voltage (IR) drop analysis and design closure: Issues and challenges

2. External Loopback Testing Experiences with High Speed Serial Interfaces

3. Designing on-chip clock generators

4. A Concurrent BIST Architecture for Combinational Logic Circuits

5. A Tunable Concurrent BIST Design Based on Reconfigurable LFSR

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