A Methodology for Handling Complex Functional Constraints for Large Industrial Designs-Reference-Cited by-同舟云学术

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A Methodology for Handling Complex Functional Constraints for Large Industrial Designs

Published:2008-02-06 Issue:1-3 Volume:24 Page:259-269
ISSN:0923-8174
Container-title:Journal of Electronic Testing
language:en
Short-container-title:J Electron Test

Author:

Jas Abhijit,Chang Yi-Shing,Chakravarty Sreejit

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering

Link

http://link.springer.com/content/pdf/10.1007/s10836-007-5024-4.pdf

Reference37 articles.

1. Abramovici M, Breuer MA, Friedman AD (1995) Digital systems testing and testable design”. John Wiley & Sons

2. Agrawal VD, Chakradhar ST (Sept. 1995) Combinational ATPG theorems for identifying untestable faults in sequential circuits. IEEE Trans Comput-Aided Des 14(9):1155–1160

3. Bryant R (1986) Graph-based algorithms for Boolean function manipulation. Proc IEEE Trans Comput 35(8):677–691

4. Chen G, Reddy SM, Pomeranz I (2003) Procedures for identifying untestable and redundant transition faults in synchronous sequential circuits. Proceedings of IEEE International Conference on Computer Design, pp. 36–41

5. Cummins CE (1999) full_case parallel_case. the Evil Twins of Verilog Synthesis. Proc Synopsys Users Group (SNUG)

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Functional Constraint Extraction From Register Transfer Level for ATPG;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2015-02

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