Formalization of Cadence SPW Fixed-Point Arithmetic in HOL-Reference-Cited by-同舟云学术

Formalization of Cadence SPW Fixed-Point Arithmetic in HOL

Published:2002 Issue: Volume: Page:185-204
ISSN:0302-9743
Container-title:Lecture Notes in Computer Science
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Author:

Akbarpour Behzad,Dekdouk Abdelkader,Tahar Sofiène

Publisher

Springer Berlin Heidelberg

Link

http://link.springer.com/content/pdf/10.1007/3-540-47884-1_11

Reference23 articles.

1. M. D. Aagaard, and C.-J. H. Seger, The formal Verification of a Pipelined Double-Precision IEEE Floating-Point Multiplier, In ICCAD, pages 7–10. IEEE, Nov. 1995.

2. G. Barrett, “Formal Methods Applied to a Floating Point Number System”, IEEE Transactions on Software Engineering, SE-15(5): 611–621, May 1989.

3. C. Berg and C. Jacobi, “Formal Verification of the VAMP Floating Point Unit”, Proc. 11th Advanced Research Working Conference on Correct Hardware Design and Verification Methods, CHARME 2001:325–339.

4. V. A. Carreno, “Interpretation of IEEE-854 Floating-Point Standard and Definition in the HOL System”, NASA Technical Memorandum 110189, September 1995.

5. M. Cornea-Hasegan, “Proving the IEEE Correctness of Iterative Floating-Point Square Root, Divide, and Remainder Algorithms”, Intel Technology Journal, Q2, 1998.

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