A Methodology for the Formal Verification of FFT Algorithms in HOL-Reference-Cited by-同舟云学术

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A Methodology for the Formal Verification of FFT Algorithms in HOL

Published:2004 Issue: Volume: Page:37-51
ISSN:0302-9743
Container-title:Formal Methods in Computer-Aided Design
language:
Short-container-title:

Author:

Akbarpour Behzad,Tahar Sofiène

Publisher

Springer Berlin Heidelberg

Link

http://link.springer.com/content/pdf/10.1007/978-3-540-30494-4_4

Reference32 articles.

1. Lecture Notes in Computer Science;B. Akbarpour,2002

2. Lecture Notes in Computer Science;B. Akbarpour,2003

3. Lecture Notes in Computer Science;B. Akbarpour,2004

4. Lecture Notes in Computer Science;P. Bjesse,1999

5. Boulton, R., Gordon, A., Gordon, M., Harrison, J., Herbert, J., Van-Tassel, J.: Experience with Embedding Hardware Description Languages in HOL. In: Theorem Provers in Circuit Design, pp. 129–156. North-Holland, Amsterdam (1992)

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