Multiple fault analog circuit testing by sensitivity analysis-Reference-Cited by-同舟云学术

Multiple fault analog circuit testing by sensitivity analysis

Published:1993-11 Issue:3 Volume:4 Page:231-243
ISSN:0925-1030
Container-title:Analog Integrated Circuits and Signal Processing
language:en
Short-container-title:Analog Integr Circ Sig Process

Author:

Hamida Naim Ben,Kaminska Bozena

Publisher

Springer Science and Business Media LLC

Subject

Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing

Link

http://link.springer.com/content/pdf/10.1007/BF01239076.pdf

Reference14 articles.

1. L. Milor and V. Visavanathan, ?Detection of catastrophic faults in analog circuits,?IEEE Trans. Comput. Aided Design, Vol. CAD-8, No. 2, pp. 114?130, 1989.

2. K.R. Chin, ?Functional testing of circuits and SMD bords with limited nodal access,? inInt. Test Conf., Los Alamitos, CA, pp. 129-143, 1989.

3. H. Dai and M. Sounders, ?Time-domain testing strategies and fault diagnosis for analog systems,?IEEE Trans. Instrum. Measure., Vol. 39, No. 1, pp. 157?162, 1990.

4. P.P. Fasang, D. Mullins, and T. Wong, ?Design for testability for mixed analog/digital ASICs,?IEEE Custom Integrated Circuits Conf., pp. 16.5.1-16.5.4, 1988.

5. Naim Ben Hamida and Bozena Kaminska, ?Analog circuit testing based on sensitivity computation and new circuit modeling,? inInt. Test Conf., Baltimore, 1993.

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