1. Hayashi, Y.: Impacts of low-k film on sub-100 nm-node, ULSI devices. IEEE Intl. Interconnect Tech. Conf., San Francisco, USA 145 (2002)
2. Takahashi, S.; Edahiro, M.; and Hayash, Y.: Interconnect design strategy: Structures, repeaters and materials with strategic system performance analysis (S 2 PAL) model. IEEE Trans. Electron Devices 48(2) 239, (2001)
3. Davis, J. A. and Meindl, J. D.: Interconnect Technology and Design for Gigascale Integration. Kluwer Academic Publishers, Dordrecht (2003)
4. Ueki, M.; Narihiro, M.; Ohtake, H.; Tagami, M.; Tada, M.; Ito, F.; Harada, Y.; Abe, M.; Inoue, N.; Arai, K.; Takeuchi, T.; Saito, S.; Onodera, T.; Furutake, N.; Hiroi, M.; Sekine, M.; and Hayashi, Y.: Highly reliable, 65 nm-node Cu dual Damascene interconnects with full porous-SiOCH (k=2.5) films for low-power ASICs. Symposium on VLSI Technology, Digest 60 (2004)
5. Tada, M.; Harada, Y.; Tamura, T.; Inoue, N.; Ito, F.; Yoshiki, M.; Ohtake, H.; Narihiro, M.; Tagami, M.; Ueki, M.; Hijioka, K.; Abe, M.; Takeuchi, T.; Saito, S.; Onodera, T.; Furutake, N.; Arai, K.; Fujii, K.; and Hayashi, Y.: A 65 nm-node, Cu interconnect technology using porous SiOCH film (k=2.5) covered with ultra-thin, low-k pore seal (k=2.7). IEEE IEDM2003, Technical Digest 35.2.1 (2003)