Redundancy
Author:
Publisher
Springer New York
Link
http://link.springer.com/content/pdf/10.1007/978-1-4419-7958-2_2
Reference57 articles.
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3. S. Fujii, K. Natori, T. Furuyama, S. Saito, H. Toda, T. Tanaka and O. Ozawa, “A low-power sub 100 ns 256K bit dynamic RAM,” IEEE J. Solid-State Circuits, vol. SC-18, pp. 441–446, Oct. 1983.
4. Y. Nishimura, M. Hamada, H. Hidaka, H. Ozaki and K. Fujishima, “A redundancy test-time reduction technique in 1-Mbit DRAM with a multibit test mode,” IEEE J. Solid-State Circuits, vol. 24, pp. 43–49, Feb. 1989.
5. M. Horiguchi, J. Etoh, M. Aoki, K. Itoh and T. Matsumoto, “A flexible redundancy technique for high-density DRAMs,” IEEE J. Solid-State Circuits, vol. 26, pp. 12–17, Jan. 1991.
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