Electrical Device Characterisation on Ultra-thin Chips
Author:
Publisher
Springer New York
Link
http://link.springer.com/content/pdf/10.1007/978-1-4419-7276-7_20
Reference17 articles.
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3. Bufler FM (2004) Exploring the limit of strain-induced performance gain in p- and n-SSDOI-MOSFETs. In: IEDM Tech Dig., San Francisco, pp. 601–604
4. Thompson SE, Armstrong M, Auth C et al. (2004) A 90-nm logic technology featuring strained-silicon. IEEE Trans Electron Dev 51(4):191–193
5. Bradley AT, Jaeger RC, Suhling JC, O’Connor KJ (2001) Piezoresistive characteristics of short-channel MOSFETs on (100) silicon. IEEE Trans Electron Dev 48(9):2009–2015
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