Increasing Reliability Using Adaptive Cross-Layer Techniques in DRPs: Just-Safe-Enough Responses to Reliability Threats

Abstract

AbstractThe developments in the semiconductor industry as predicted by institutions such as the ITRS present a difficult question to hardware and software developers alike: How to implement increasingly complex, power hungry, and critical applications reliably in today’s and tomorrow’s semiconductor technology? The present trend of semiconductor technology is characterized by a sharp increase in complexity, cost, and delicacy. Also, it does not scale along the demands which are still based on and often exceed Moore’s Law. In this chapter, we propose to exploit the architectural redundancies provided by potent, yet energy efficient massively parallel architectures, modeled using Dynamically Reconfigurable Processors (DRP). Using DRPs, we built an extensive cross-layer approach, offering different levels of reliability measures to operating system (OS) and software developers through low-cost hardware redundancy schemes and appropriate physical operating condition tuning. On the hardware side, online testing schemes and error detection are deployed to trigger dynamic remapping to avoid the usage of faulty components. This approach is further complemented through hardware health monitoring that can detect reliability issues such as negative bias temperature instability (NBTI) or hot carrier injection (HCI) before they surface as an error as well as further tuning of operating conditions to delay such phenomena from surfacing.