Author:
Ushenina I. V.,Chirkova E. V.
Publisher
Springer International Publishing
Reference15 articles.
1. Ercegovac, M.D., Lang, T.: Digital Arithmetic. Elsevier (2004)
2. Malik, A., Ko, S.B.: A study on the floating-point adder in FPGAs. In: 2006 Canadian Conference on Electrical and Computer Engineering, pp. 86–89. IEEE (2006)
3. Shirke, M., Chandrababu, S., Abhyankar, Y.: Implementation of IEEE 754 compliant single precision floating-point adder unit supporting denormal inputs on Xilinx FPGA. In: 2017 IEEE International Conference on Power, Control, Signals and Instrumentation Engineering (ICPCSI), pp. 408–412. IEEE (2017)
4. Shirazi, N., Walters, A., Athanas, P.: Quantitative analysis of floating point arithmetic on FPGA based custom computing machines. In: Proceedings IEEE Symposium on FPGAs for Custom Computing Machines, pp. 155–162. IEEE (1995)
5. Beauchamp, M.J., Hauck, S., Underwood, K.D., Hemmert, K.S.: Architectural modifications to enhance the floating-point performance of FPGAs. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 16(2), 177–187 (2008)