A Study on the Floating-Point Adder in FPGAS-Reference-Cited by-同舟云学术

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A Study on the Floating-Point Adder in FPGAS

Published:2006 Issue: Volume: Page:
ISSN:
Container-title:2006 Canadian Conference on Electrical and Computer Engineering
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Author:

Malik Ali,Ko Seok-bum

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/4054516/4054517/04054889.pdf?arnumber=4054889

Cited by 5 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Designing an IEEE-Compliant FPU that Supports Configurable Precision for Soft Processors;ACM Transactions on Reconfigurable Technology and Systems;2024-04-30

2. FPGA Implementation of a High Speed Efficient Single Precision Floating Point ALU;2023 International Conference on Control, Communication and Computing (ICCC);2023-05-19

3. Floating Multiplier based Matrix Multiplication using PPI-MO Technique;2023 7th International Conference on Intelligent Computing and Control Systems (ICICCS);2023-05-17

4. A High Performance and Full Utilization Hardware Implementation of Floating Point Arithmetic Units;2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS);2021-11-28

5. Implementing Sticky Bit Generators Based on FPGA Carry-Chains for Floating-Point Adders;Advances in Intelligent Systems and Computing;2020

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