Implementation of IEEE 754 compliant single precision floating-point adder unit supporting denormal inputs on Xilinx FPGA-Reference-Cited by-同舟云学术

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Implementation of IEEE 754 compliant single precision floating-point adder unit supporting denormal inputs on Xilinx FPGA

Published:2017-09 Issue: Volume: Page:
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Container-title:2017 IEEE International Conference on Power, Control, Signals and Instrumentation Engineering (ICPCSI)
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Author:

Shirke Milind,Chandrababu Sajish,Abhyankar Yogindra

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8385064/8391768/08392326.pdf?arnumber=8392326

Cited by 5 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Simple Numerical Solution Framework for Ordinary Differential Equations Based on Reduced MIPS Instructions;2022 IEEE 4th International Conference on Circuits and Systems (ICCS);2022-09-23

2. An area efficient FFT and its hardware implementation;Journal of Information and Optimization Sciences;2022-04-03

3. A High Performance and Full Utilization Hardware Implementation of Floating Point Arithmetic Units;2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS);2021-11-28

4. Implementing Sticky Bit Generators Based on FPGA Carry-Chains for Floating-Point Adders;Advances in Intelligent Systems and Computing;2020

5. Multi-input multiplexers and selectors as basic shifter blocks in arithmetic devices operating in floating point: comparative analysis;Journal of Physics: Conference Series;2019-12-01

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