HSCS: a hybrid shared cache scheduling scheme for multiprogrammed workloads

Author:

Zhang Jingyu,Wu Chentao,Yang Dingyu,Chen Yuanyi,Meng Xiaodong,Xu Liting,Guo Minyi

Publisher

Springer Science and Business Media LLC

Subject

General Computer Science,Theoretical Computer Science

Reference49 articles.

1. Chou C, Jaleel A, Qureshi M K. BEAR: techniques for mitigating bandwidth bloat in gigascale DRAM caches. In: Proceedings of the 42nd Annual International Symposium on Computer Architecture. 2016, 198–210

2. Lee Y, Kim J, Jang H, Yang H, Kim J, Jeong J, Lee J W. A fully associative, tagless DRAM cache. In: Proceedings of ACM/IEEE International Symposium on Computer Architecture. 2015, 211–222

3. Hameed F, Bauer L, Henkel J. Adaptive cache management for a combined SRAMand DRAM cache hierarchy for multi-cores. In: Proceedings of Design, Automation and Test in Europe. 2013, 77–82

4. Hundal R, Oklobdzija V G. Determination of optimal sizes for a first and second level SRAM-DRAM on-chip cache combination. In: Proceedings of IEEE International Conference on Computer Design: VLSI in Computers and Processors. 1994, 60–64

5. Qureshi M K, Loh G H. Fundamental latency trade-off in architecting DRAM caches: outperforming impractical SRAM-tags with a simple and practical design. In: Proceedings of IEEE/ACM International Symposium on Microarchitecture. 2012, 235–246

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