1. Liang H, Xia Y S, Qian L B, Huang C L. Low power 3-input AND/XOR gate design. Journal of Computer-Aided Design & Computer Graphics, 2015, 27(5): 940–945
2. Wang X, Lu Y, Zhang Y. Probabilistic modeling during power estimation for mixed polarity Reed-Muller logic circuits. In: Proceedings of IEEE International Conference on Green Computing and Communications. 2013, 1414–1418
3. Wang P J, Wang Z H, Xu R. Conversion algorithm for MPRM expansion. Journals of Semiconductors, 2014, 35(3): 150–155
4. Bu D L, Jiang J H. An efficient optimization algorithm for multi-output MPRM circuits with very large number of input variables. In: Proceedings of the 7th IEEE Joint International Information Technology and Artificial Intelligence Conference. 2014, 228–232
5. Geetha V, Devarajan N, Neelakantan P N. OR-Bridging fault analysis and diagnosis for exclusive-OR sum of products Reed-Muller canonical circuits. Journal of Computer Science, 2011, 7(5): 744–748