An Efficient and Fast Area Optimization Approach for Mixed Polarity Reed-Muller Logic Circuits

Author:

Zhou Yuhao1,He Zhenxue2,Jiang Jianhui1,Zhao Xiaojun2,Zhang Fan2,Xiao Limin3,Wang Xiang4

Affiliation:

1. School of Software Engineering, Tongji University,Shanghai,China,201804

2. Hebei Agricultural University,Key Laboratory of Agricultural Big Data of Hebei Province,Baoding,China,071001

3. School of Computer Science and Engineering, Beihang University,Beijing,China,100191

4. School of Electronic and Information Engineering, Beihang University,Beijing,China,100191

Funder

National Natural Science Foundation of China

Natural Science Foundation of Hebei Province

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Reference45 articles.

1. Logic gates based on neuristors made from two-dimensional materials

2. A Low-Area and Low-Power Comma Detection and Word Alignment Circuits for JESD204B/C Controller

3. Managing the impact of increasing microprocessor power consumption;Gunther;Intel Technology Journal,2001

4. An Analog Control Strategy With Multiplier-Less Power Calculation Circuit for Flyback Microinverter

5. Low power 3-input AND/XOR gate design;Liang;Journal of Computer-Aided Design & Computer Graphics,2015

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