1. V. Chan, R. Rengarajan, N. Rovedo, W. Jin, T. Hook, P. Nguyen et al., “High speed 45 nm gate length CMOSFETs integrated into a 90 nm bulk technology incorporating strain engineering,” in Electron Devices Meeting, 2003. IEDM’03 Technical Digest. IEEE International (2003), pp. 3.8.1–3.8.4
2. P. Bai, C. Auth, S. Balakrishnan, M. Bost, R. Brain, V. Chikarmane et al., “A 65 nm logic technology featuring 35 nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 µm 2 SRAM cell” in Electron Devices Meeting (2004). IEEE International, pp. 657–660
3. P. Chidambaram, B. Smith, L. Hall, H. Bu, S. Chakravarthi, Y. Kim et al., “35 drive current improvement from recessed-SiGe drain extensions on 37 nm gate length PMOS,” in VLSI Technology, pp. 48–49 (2004)
4. S.E. Thompson, M. Armstrong, C. Auth, S. Cea, R. Chau, G. Glass et al., “A logic nanotechnology featuring strained-silicon”. Electron Device Lett. 25, 191–193 (2004)
5. S. Thompson, N. Anand, M. Armstrong, C. Auth, B. Arcot, M. Alavi et al., “A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1/spl mu/m/sup 2/SRAM cell” in Electron Devices Meeting (2002). IEEE International, pp. 61–64