Author:
Majumder Subhashis,Bhattacharya Bhargab B.,Agrawal Vishwani D.,Bushnell Michael L.
Publisher
Springer Science and Business Media LLC
Subject
Computational Theory and Mathematics,Computer Science Applications,Hardware and Architecture,Theoretical Computer Science,Software
Reference24 articles.
1. Krstić A, Cheng K T. Delay Fault Testing for VLSI Circuits. Boston: Kluwer Academic Publishers, 1998.
2. Lin C J, Reddy S M. On delay fault testing in logic circuits.IEEE Trans. CAD, Sept. 1987, 6: 694–703.
3. Smith G L. Model for delay faults based upon paths. InProc. International Test Conf., Oct. 1985, pp.342–349.
4. Aitken R C. Nanometer technology effects on fault models for IC testing.IEEE Trans. Computers, Jan. 1999, 48: 46–51.
5. Needham W N, Prunty C, Yeoh E H. High volume microprocessor test escapes, an analysis of defects our tests are missing. InProc. International Test Conf., Oct. 1998, pp.25–34.
Cited by
2 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献