Author:
Agrawal Anshul,Khatri Rajesh
Publisher
Foundation of Computer Science
Cited by
7 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Design and Implementation of PLL with Dead Zone-Less Low-Power Phase Frequency Detector;International Journal of Innovative Science and Research Technology (IJISRT);2024-07-16
2. Self-cascode and self-biased Dickson charge pump for fast locking wide lock range PLL with reduced phase noise;Engineering Research Express;2024-04-25
3. Design and Linearity Analysis of a Dual Control 5-Stage CSR-VCO for RF Applications;2024 3rd International Conference on Advancement in Electrical and Electronic Engineering (ICAEEE);2024-04-25
4. Design of Charge Pump for Low Power, Wide Range PLL in 65nm CMOS Technology;2023 22nd International Symposium on Communications and Information Technologies (ISCIT);2023-10-16
5. Design and Analysis of Low-Power PLL for Digital Applications;International Conference on Advanced Computing Networking and Informatics;2018-11-28