VERILOG_A IMPLEMENTATION OF NANOWIRE JUNCTIONLESS ISFET COMPACT MODEL AND READ-OUT CIRCUIT DESIGN-Reference-Cited by-同舟云学术

VERILOG_A IMPLEMENTATION OF NANOWIRE JUNCTIONLESS ISFET COMPACT MODEL AND READ-OUT CIRCUIT DESIGN

Published:2022 Issue: Volume: Page:
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Author:

YEZAKYAN N.D.,YESAYAN A.E.,SALLESE J-M.

Abstract

In this paper, we implement nanowire (NW) junctionless (JL) ISFET model in Verilog-A hardware language. The Verilog-A implementation would allow the NW ISFET integration with signal processing circuits. The simulated by the code pH values are compared with the corresponding data from COMSOL simulations, and a good agreement is observed. The readout circuit based on amperometric switched- capacitors schemes is designed. The readout circuit has introduced good linearity in pH values range from 3 to 7.

Publisher

National Polytechnic University of Armenia

Subject

General Earth and Planetary Sciences,General Environmental Science,General Medicine,General Earth and Planetary Sciences,General Environmental Science,General Medicine,General Medicine,General Medicine,General Medicine,Rehabilitation,Physical Therapy, Sports Therapy and Rehabilitation,General Medicine,Geology,Ocean Engineering,Water Science and Technology,General Medicine

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